In recent years, in power semiconductor devices, such as an IGBT (insulated gate bipolar transistor), a MOSFET (MOS field effect transistor), and a diode which are provided in inverters, the thickness of a silicon substrate for forming the power semiconductor device has been reduced in order to improve the electrical characteristics of the power semiconductor device.
FIG. 13 is a diagram illustrating the cross-sectional structure of a main portion of an FS (Field Stop)-IGBT. In FIG. 13, the FS-IGBT includes a p well layer 52 that is provided (formed) in a surface layer of an n silicon substrate 51d (when a wafer 51 is cut into chips) with a thickness of about 150 μm and a trench 53 that passes through the p well layer 52.
In addition, the FS-IGBT includes an n emitter layer 54 that is provided in a surface layer of the p well layer 52 so as to come into contact with the trench 53. A gate oxide film 55 is provided on the inner wall of the trench 53 and a gate electrode 56 is provided in the trench 53 through the gate oxide film 55.
An interlayer insulating film 57 is provided on the gate electrode 56 and an emitter electrode 58 is provided on the interlayer insulating film 57 so as to be electrically connected to the n emitter layer 54. An n-FS layer 60 and a p collector layer 61 are provided on the rear surface of the n silicon substrate 51d and a collector electrode 62 is provided on the p collector layer 61 so as to be electrically connected thereto. Next, a process of manufacturing the FS-IGBT will be described.
(1) A surface structure including, for example, the p well layer 52, the n emitter layer 54, the gate electrode 56, and an aluminum electrode 58a (which is a front electrode and is a portion of the emitter electrode 58) is formed on the front surface of a thick wafer. The interlayer insulating film 57 is formed on the gate electrode 56 and the aluminum electrode 58a is formed on the interlayer insulating film 57.
(2) A protective tape is attached to the front surface of the thick wafer and the rear surface of the thick wafer is ground. Then, the protective tape peels off and wet etching is performed on a grinding surface to remove a fractured layer. In this way, a thin wafer 51 with a thickness of about 150 μm is obtained.
(3) Phosphorous (P) and boron (B) ions are implanted into the rear surface and annealing is performed to form an n-FS layer 60 and a p collector layer 61.
(4) Polyimide 76 is applied onto the entire upper surface of the wafer 51 and the polyimide 76 on the emitter electrode 58 of an effective chip 71 is removed (see (a) of FIG. 14). FIG. 14 is a diagram illustrating a wafer according to the related art. In FIG. 14, (a) is a plan view illustrating a portion 77 of the wafer according to the related art in which only polyimide on an emitter electrode of an effective chip is removed, (b) is a cross-sectional view illustrating a main portion taken along the line X1-X1 of (a), and (c) is a cross-sectional view illustrating a main portion taken along the line X2-X2 of (a).
In (b) and (c) of FIG. 14, reference numeral 74 indicates the center line of a dicing line 73 and reference numeral 57a indicates an insulating film that covers the breakdown voltage structure of an IGBT and the dicing line 73. In addition, in (a) and (c) of FIG. 14, the leading end of a lead line A is the end of the exposed emitter electrode and indicates the emitter-electrode-side end of the polyimide 76 and the leading end of a lead line B is the end of the dicing line 73 and indicates the end of the polyimide 76.
In the polyimide 76 which is applied onto the entire upper surface of the wafer 51, when the polyimide 76 on the emitter electrode 58 of the effective chip 71 is removed (see (a) of FIG. 14), the polyimide 76 on the dicing line 73 which partitions the effective chips 71 is also removed and the insulating film 57a on the dicing line 73 is exposed (see (c) of FIG. 14). On the other hand, the insulating film 57a is covered with the polyimide 76 on the dicing line 73 which partitions the ineffective chips 72 (see (b) of FIG. 14).
The effective chip 71 means an available chip when chips are arranged at the center of the wafer 51. The ineffective chip 72 means a chip which is arranged in the outer circumference of the wafer 51 and is not available as an element since the edge thereof is chipped off or since a necessary process, such as deposition, is not completely performed.
(5) The collector electrode 62, which is a rear electrode, is formed on the rear surface of the wafer 51 by sputtering.
(6) A nickel film 58b and a gold film 58c are formed only on the aluminum electrode 58a on the surface surrounded by the end 76b of the polyimide 76 by electroless plating to form the emitter electrode 58 (see (c) of FIG. 14). This is needed in order to solder the emitter electrode 58 to an external lead conductor. As illustrated in (c) of FIG. 14, the polyimide on the dicing line 73 is also removed. However, since the insulating film 57a is exposed, the nickel film 58b and the gold film 58c are not deposited by electroless plating.
(7) The wafer 51 is diced into chips along the dicing lines 73 by a blade 82 (see FIG. 17).
Next, the reason why the outer circumferential portion of the wafer 51 and a portion other than the effective chips 71 are covered with the polyimide 76 in the above-mentioned process will be described. FIG. 15 is a diagram illustrating the structure of the wafer subjected to edge rinse and FIG. 16 is a diagram illustrating the structure of the wafer on which polyimide is not formed. In FIG. 15, (a) is a plan view illustrating a main portion and (b) is a cross-sectional view illustrating the main portion taken along the line X-X of (a). In FIG. 15, reference numeral 55a indicates an oxide film that is formed at the same time as the gate oxide film 55 is formed, reference numeral 56a indicates a polyimide film that is formed at the same time as the gate electrode 56 is formed, reference numeral 57a indicates an insulating film that is formed at the same time as the interlayer insulating film 57 is formed, and reference numeral 58d indicates an aluminum film that is formed at the same time as the aluminum electrode 58a is formed.
(Reason 1) As illustrated in FIG. 15, edge rinse 90 is performed on the outer circumferential portion of the wafer 51 and, for example, silicon forming the wafer 51, a polysilicon film for forming the gate electrode 56, and a BPSG film, which is the interlayer insulating film 57 are exposed from the outer circumferential portion of the wafer 51. The edge rinse 90 is a process of removing a photoresist which covers the outer circumferential portion of the wafer 51.
As such, when various films formed on the wafer 51 are exposed from the outer circumferential portion by the edge rinse 90, plating metal is abnormally deposited on a conductive film, such as the polysilicon film 56a or the aluminum film 58d in the plating process. When an abnormal deposit 91 peels off and is attached to the surface of a semiconductor chip (hereinafter, simply referred to as a chip) during the plating process or in the subsequent process, the reliability of the manufactured semiconductor device, such as an FS-IGBT, is reduced. In order to prevent the reduction in the reliability, the outer circumferential portion of the wafer 51 is covered with the polyimide 76 such that the outer circumferential portion of the wafer 51 is not plated.
(Reason 2) As illustrated in FIG. 16, when the entire surface of the wafer 51 is not covered with the polyimide 76, the aluminum electrode 58a of the ineffective chip 72 is plated with plating metal 92 (for example, a nickel film or a metal film). As a result, the region to be plated increases and the chemical life of a plating solution is reduced, which results in an increase in manufacturing costs. In order to solve the problems, a portion other than the effective chip 71 is covered with the polyimide 76. However, the insulating film 57a covers the breakdown voltage structure 70 and the dicing line 73.
Patent Document 1 (identified further on) discloses a technique which forms a passivation film made of a resist on the main surface of a wafer in which a plurality of chips are formed so as to be separated from each other by dicing lines, removes the passivation film on the dicing lines while leaving the passivation film in a region that is several millimeters away from the outer circumferential portion of the wafer, attaches a protective tape to the main surface of the wafer, and grinds the rear surface of the water. In this way, the gap between the dicing line and the protective tape is closed until it reaches the outer circumferential portion of the wafer and the infiltration of abrasive water is prevented when the rear surface of the wafer is ground. Therefore, it is possible to prevent a pad portion of the chip from being contaminated due to Si scrap caused by the mixture of the abrasive water.